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industrial & multimarket preliminary data sheet revision 1.0, 2011-03-30 ISO1I813T isolated 8 channel digital input with iec61131-2 type 1/2/3 characteristics isoface?
edition 2011-03-30 published by infineon technologies ag 81726 munich, germany ? 2011 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
preliminary data sheet 3 v1.0, 2011-03-30 ISO1I813T ISO1I813T revision history: 2011-03-30, v1.0 previous version: page subjects (major cha nges since last revision) preliminary datasheet
ISO1I813T preliminary data sheet 4 v1.0, 2011-03-30
preliminary data sheet 5 v1.0, 2011-03-30 ISO1I813T 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-8 1.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-8 1.2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-10 1.2.1 pins of sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-10 1.2.2 pins of serial and parallel logic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-11 2blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p ds-13 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-14 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-14 3.2 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-14 3.2.1 voltage limits on vbb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-15 3.2.2 external supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-16 3.2.3 dc/dc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-17 3.3 internal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-20 3.4 sensor input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-21 3.4.1 input type select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-21 3.4.2 wire break detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-23 3.5 common error output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-24 3.6 programmable digital input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-26 3.7 parallel interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-27 3.8 serial interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-29 3.8.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-30 3.8.2 architecture of crc-engines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-34 3.9 sync operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-34 4 standard compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-35 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-37 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-37 5.2 operating conditions and power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p ds-38 5.3 electrical characteristics in put side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-40 5.4 electrical characteristics mi crocontroller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p ds-42 6 registers of microcon troller-interface-chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-46 6.1 controller chip registers over view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-46 6.2 presentation of the registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-47 6.2.1 sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-47 6.2.2 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-47 6.2.3 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-48 6.3 controller registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-49 6.3.1 collective diagnostics register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-49 6.3.2 input channel data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-49 6.3.3 global error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-50 6.3.4 filter time of channel 0-7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-51 6.3.5 internal error register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-52 6.3.6 global configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-53 7 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pds-5 4
ISO1I813T preliminary data sheet 6 v1.0, 2011-03-30
preliminary data sheet 7 v1.0, 2011-03-xx ISO1I813T isolated 8 channel digital input with iec61131-2 type 1/2/3 characteristics product highlights ? minimization of power dissipa tion due to constant current characteristic ? status led output for each input ? digital averaging of the input signals to suppress interference pulses ? isolation between input and output using coreless transformer technology c e.g. xe166 i0h i0l gndbb i7h i7l vbb vcc ts /err gnd s e r i a l i z e d e s e r i a l i z e l o g i c ISO1I813T parallel or serial interface digital filter digital filter 8 sensors 2k 12k 330n 2k 12k in0 in7 v fi gndfi sync wb sw1 sw2 dc ena /cs rosc typical application for sensor of type 1/3 features ? complete system integration (digital sensor or switch input, galvanic isolation and intelligent micro-controller or bus-asic interface ? 8-channel input according to iec61131-2 (type 1/2/3) ? integrated galvanic isolation 500vac (en60664-1, ul508) ? 5/3.3v spi and parallel micro-controller interface ? adjustable deglitching filters ? up to 500 khz sampling frequency ? wire-break detection ? vbb under-voltage detection ? package: tssop 8 x 12.5 mm typical application programmable logic controllers(plc) industrial pc general control equipment description the ISO1I813T is an electrically isolated 8 bit data input interface in tssop-48 package. this part is used to detect the signal states of eight independent input lines according to iec61131-2 type 1/2/3 (e.g. two-wire proximity switches) with a common ground (gndfi). for operating sensors of type 1/2/3 in accordance with iec61131-2, it is necessary for the device to be wired with resistors r v and r ext (it is recommended to use resistors with an accuracy of 2%, in any case < 5% - is mandatory, temperature- coefficients < 200ppm are allowed). the figure below shows the typical application circuit for type 1/3. an 8 bit parallel c compatib le interface allows to connect the ic directly to a c system. the input interface supports also a direct control mode and is designed to operate with 3.3/5v cmos compatible levels. the data transfer from input to output side is realized by the integrated coreless transform er technology.
ISO1I813T pin configuration and functionality preliminary data sheet 8 v1.0, 2011-03-xx 1 pin configuration and functionality the pin configuration slightly differs for the parallel or the serial interfaces. 1.1 pin configuration the ordering, type and functions of the ic pins are listed in the table 1 . table 1 pin configuration pin parallel interface mo de serial interface mode symbol ctrl 1) type 2) function symbol ctrl. type function asic / micro-controller side pins 1 gnd a logic ground gnd 2 sel i pd serial parallel mode select sel 3 sync i pu freeze data & diagnostics sync 4 rosc a clock frequency adjustment rosc 5 vcc a positive 5/3.3v logic supply vcc 6err od, pu fault indication output err 7 gnd a logic ground gnd 8 ad0 io ppz data output bit0 sdi i pd spi data input 9 ad1 io ppz data output bit1 sso o ppz spi status output 10 ad2 io ppz data output bit2 gnd 11 ad3 io ppz data output bit3 gnd 12 ad4 io ppz data output bit4 crcerr od, pu crc error output 13 ad5 io ppz data output bit5 sclk i pd spi shift clock input 14 ad6 io ppz data output bit6 ssi i pd spi status input 15 ad7 io ppz data output bit7 sdo o ppz spi data output 16 cs ipuchip select cs 17 rd i pu data read n.c. 18 gnd a logic ground gnd 19 w r i pu data write ms0 i pd spi mode select bit 0 20 ale i pd address latch enable ms 1 i pd spi mode select bit 1 21 dc_ena i pd dc-dc supply enable dc_ena 22 sw1 a dc-dc switch output 1 sw1 23 sw2 a dc-dc switch output 2 sw2 24 gnd a logic ground gnd sensor side pins 25 gndbb a input ground gndbb 26 vbb a positive input supply voltage vbb 27 i0l a input 0 low, led out i0l 28 i0h a input 0 high i0h 29 i1l a input 1 low, led out i1l
preliminary data sheet 9 v1.0, 2011-03-xx ISO1I813T pin configuration and functionality 30 i1h a input 1 high i1h 31 gndbb a input ground gndbb 32 i2l a input 2 low, led out i2l 33 i2h a input 2 high i2h 34 i3l a input 3 low, led out i3l 35 i3h a input 3 high i3h 36 ts a sensor type 1/2/3 select ts 37 gndbb a input ground gndbb 38 wb a wire break select wb 39 i4l a input 4 low, led out i4l 40 i4h a input 4 high i4h 41 i5l a input 5 low, led out i5l 42 i5h a input 5 high i5h 43 gndbb a input ground gndbb 44 i6l a input 6 low, led out i6l 45 i6h a input 6 high i6h 46 i7l a input 7 low, led out i7l 47 i7h a input 7 high i7h 48 gndbb a input ground gndbb 1) direction of the pin: i = i nput, o = output, io = input/output 2) type of the pin: a = analog, d = open-drain, pu = internal pull-up resistor, pd = internal pull-down resistor, ppz = push- pull pin with high-impedance functionality table 1 pin configuration pin parallel interface mode serial interface mode symbol ctrl 1) type 2) function symbol ctrl. type function
ISO1I813T pin configuration and functionality preliminary data sheet 10 v1.0, 2011-03-xx figure 1 tssop-48 pinout for parallel and serial interface modes 1.2 pin functionality 1.2.1 pins of sensor interface vbb (positive supply 9.6-35v sensor supply) vbb supplies the sens or input stage. gndbb (ground for vbb domain) this pin acts as the ground refere nce for the sensor input st age that is supplied by vbb. i0h... i7h (input channel 0 ... 7) sensor inputs with current sink characteristic accordi ng iec61131-2 type 1/2/3 whic h has been selected by pin ts i0l... i7l (led output channel 0 ... 7) this pin provides the output signal to switch on the led if the input voltage and current has been detected as ?high? according to the selected sensor type. wb (wire-break select) by connecting a resistor between wb and gndbb, the level for the wire-b reak detection can be adjusted (refer to table 10 ). this pin is for static conf iguration (pin-strapping). the input voltage must not change during operation. ts (type select) by connecting a resistor between ts and gndbb the sensor type (type 1/ 2/3) can be selected (refer to table 10 for corresponding resistor value). this pin is for static configuration (pin-strapping). the input voltage must not change during operation. gnd sel sync rosc /err gnd ad0 ad1 ad3 ad4 ad5 ad6 ad7 /cs /rd gnd ad2 /wr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 gndbb i6h i6l wb i5h i5l i4h gndbb gndbb i3h i7h i7l i2h i3l i2l i4l ts 36 35 34 33 32 31 30 29 28 27 26 25 pinout for parallel interface ale vcc dc_ena sw 1 sw 2 gnd 19 20 21 22 23 24 i1h i1l i0l i0h vbb gndbb 44 43 42 41 40 39 38 37 48 47 46 45 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 pinout for serial interface 19 20 21 22 23 24 44 43 42 41 40 39 38 37 48 47 46 45 gnd sel sync rosc /err gnd sdi sso gnd crcerr sclk ssi sdo /cs nc gnd gnd ms0 ms1 vcc dc_ena sw1 sw2 gnd n .c. = not connected gndbb gndbb i6h i6l wb i5h i5l i4h gndbb gndbb i3h i7h i7l i2h i3l i2l i4l ts i1h i1l i0l i0h vbb gndbb gndbb
preliminary data sheet 11 v1.0, 2011-03-xx ISO1I813T pin configuration and functionality 1.2.2 pins of serial and parallel logic interface some pins are common for both interface types, some ot hers are specific for the parallel or serial access. vcc (positive 3.3/5v logic supply) vcc supplies the output interface that is electrically isol ated from the sensor input stage. the interface can be supplied with 3.3/5v. gnd (ground for vcc domain) this pin acts as the ground reference for the uc-interface that is supplied by vcc. rosc (clock adjustment) a high precision resistor has to be connected between ro sc and gnd to set the frequency of the sampling clock. dc_ena (dc-dc co nverter enable) when the dc_ena pin is connected to vcc, the internal dc -dc driver is activated. wh en dc_ena is in the state low, the switches are not driven. the input voltage must not change during operation. this pin has an internal pull-down resistor. sw1, sw2 (dc-dc switch outputs 1/2) when the dc_ena pin is connected to vcc, the outputs sw1 and sw2 switch at the clock-frequency determined by the resistor at rosc to supply the external push-pu ll converter. the switching frequency can be divided by two by setting the responsible bit in the glcfg register (see also section 6) . both outputs provide an open drain functionality. err (error) the low active err signal contains the or-wired information of the sensor input undervoltage and missing voltage detection, the internal data transmission failure detec tion unit and the overcurrent fault of the dc-dc-converter. the output pin err provides an open drain functionality. during st art up this pin is pulled to high state. this pin has an internal pull-up resistor. in normal operation the signal err is high. see section 3.5 for more details. sel (serial or para llel mode select) when this pin is in a logic low stat e, the ic operates in parallel mode. for serial mode operation the pin has to be pulled in logic high state. during start up the ic is operating in parallel mode. th is pin has an internal pull- down resistor. this pin must not change during operation. sync when this pin is in a logic high stat e, the ic operates in continuous mo de with the internal sampling clock. in isochronous mode, the inter nal data and diagnostics registers are synch ronized on each falling edge detected at sync. in logic low state the internal data and diagnostic registers are not updated. during start-up this pin is pulled to high state. this pin has an internal pull-up resistor. (see also section 3.9 cs (chip select) when this pin is in a logic low state, the ic interface is enabled and data can be transferred. this pin has an internal pull-up resistor. the following pins are provided in the parallel interface mode ad7:ad0 (addressdata input / output bit7 ... bit0) the pins ad0 .. ad7 are the bidirectio nal input / outputs for data write and read. depending on the state of the ale, rd , wr pins, register addresses or data can be transferred between the internal registers and e.g. the micro- controller. rd , wr (read / write ) by pulling one of these pins down, a read or write transa ction is initiated on the addressdata bus and the data becomes valid. these pins have internal pull-up resistors.
ISO1I813T pin configuration and functionality preliminary data sheet 12 v1.0, 2011-03-xx ale (address latch enable) the pin ale is used to select between ad dress (ale is in a logic high state) or data (ale is in a logic low state). when ale is pulled high, addresses are transferred and la tched over the bit ad0 to ad7. during the low state of ale all read or write transactions hit the same ad ress. this pin has an inte rnal pull-down resistor. the following pins are provided in the serial interface mode ms0, ms1 (serial mode select) by driving these pins to logic high or low the serial in terface mode can be selected. these pins have internal pull-down resistors. the mode of the serial interface can be changed during operation. sclk (serial interface shift clock) input data are sampled with th e rising edge and outp ut data are updated with the fa lling edge of this input clock signal. this pin has an internal pull-down resistor. sdi, ssi (serial interface data/status input ) sdi/ssi data is put into a dedicated fifo to program the filtering time and mask the wire-break diagnostic bits of each channel (spi mode 2 and 3) or to program register ad resses the contents of which to be read subsequently. this pin has an internal pull-down resistor. sdo, sso (serial interface data/status outputs) sdo provides typically the sensor data bits , sso provides the sensor diagnostic bits. crcerr (crc error output) this pin is in a logic low state when crc errors or sh ift-clock errors are detected internally. this pin has an internal pull- up resistor.
preliminary data sheet 13 v1.0, 2011-03-xx ISO1I813T blockdiagram 2blockdiagram figure 2 block diagram ISO1I813T i1h i1l i2h i2l i3h i3l i4h i4l i5h i5l i6h i6l i7h i7l sensor circuit 0 i0h i0l gndbb data diag data diag data diag data diag data diag data diag data diag data diag s e r i a l i z e mv d e s e r i a l i z e u p d a t e g a t e /err interface handler /wr ale /rd sdi ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 sclk sdo sso /crcerr parallel interface serial interface gnd uvlo vcc vali- dation uvlo vbb dc/dc sw1 sw2 tx/rx control uv ts wb dc_ena type selector wire- break selector sensor circuit 1 sensor circuit 2 sensor circuit 3 sensor circuit 4 sensor circuit 5 sensor circuit 6 sensor circuit 7 sync tx/rx control data data data data data data data data diag diag diag diag diag diag diag diag filter 7 filter 6 filter 5 filter 4 filter 3 filter 2 filter 1 filter 0 startup common error osc clk rosc /cs crc control registers ms0 ms1 sel ssi 813 t - blockdiagram
ISO1I813T functional description preliminary data sheet 14 v1.0, 2011-03-xx 3 functional description the ISO1I813T is an electrically isolated 8 bit data input interface. this part is used to detect the signal states of eight independent input lines according to iec61131-2 type 1/2/3 (e.g. two-wire proximity swit ches) with a common ground (gndbb). 3.1 introduction the current in the input circuit is determined by the switch ing element in state ?0? and by characteristics of the input stage in state ?1?. the octal input device is intended for a configuration comprising two specifie d external resistors per channel, as shown in the block diagram. as a result the power dissipation within the package is at a minimum. the voltage dependent current through the external resistor r ext is compensated by a negative differential resistance of the current sink across pins ixh and ixl, therefore input inx behaves like a const ant current sink. the comparator assigns level 1 or 0 to the voltage pres ent at input i. to improve interference protection, the comparator is provided with hyster esis. a status led is connected in series with the input circuit (r ext and current sink). if no led is used an external resistor of 2 k ? has to be connected between ixl and gndbb. the specified switching thresholds may change if the led is replaced by a resistor. the led drive short-circuits the status led if the comparator detects ?0?. a constant current sink in parallel with the led reduces the operating current of the led, and a voltage limiter ensures that the input circuit remains operational if the led is interrupted but the switching thresholds may change. for each channel an adjustable digital filter is provided which samples the comparator signal at a rate configured by programming internal registers. the digital filter is designed to provide averaging characteristics. if the input value remains the same for the selected number of samp ling values than, the output changes to the corresponding state. the c compatible interfaces allow a direct connection to the ports of a microcontroller without the need for other components. the diagnostic logic on the chip monitors the in ternal data transfer as well as the sensor input supply. the information is send via the internal coreless transformer to the pin err at the input interface 3.2 power supply the ic contains 2 electrica lly isolated voltage domains that are inde pendent from each other. the microcontroller interface is supplied via pin vcc, g nd and the input stage is supplied via pin vbb, gndbb. the different voltage domains can be switched on at different time. figure 4 shows the start up behaviour if both voltage domains are powered by an external pow er supply. if the vcc and vbb voltage have reached their operat ing range and the internal data transmission has been started successfully, the ic indicates the end of the start up procedure by setting the pin err to logic high. in the situation of a supply vo ltage drop at vbb on the sense side - even short - the sense chip requires a proper restart and theref ore the controller side control unit needs to react accordingly, especially to guarantee the integrity of the sensor data provided to the filter stage.
preliminary data sheet 15 v1.0, 2011-03-xx ISO1I813T functional description 3.2.1 voltage limits on vbb figure 3 start up procedure with external power supply during uvlo, all registers are reset to their reset values as specified in the chapter 6.2 . as a result, the flags te, uv as well as mv are high and the err pin is low (error condition). immedi ately after the reset is released, the chip is first configured by ?reading? the logic level of the sel, ms1, ms0 (when available). the ic powers up as a parallel device i.e. the ad0-7 pins are high-im pedance until the ic configuration is over. the supply voltage vbb is monitored during operation by two internal comparators (with typ. 8 s blanking time @ 500khz f scantyp ) detecting: ? vbb undervoltage: if the voltage dr ops below the uv threshold (see table 7 ), the uv-bit in the glerr register is set high. the ic operates normally. ? vbb missing voltage: if the voltage furt her drops below the mv th reshold, lower than th e previous threshold, the mv-bit in the glerr register is set, the sense side of the ic is turned off when reaching the v reset threshold whereas the micro-controller side remains active. these 2 thresholds are inactive when the ic operates in self power mode i.e. when the dc_ena pin is high. note: in case dc_ena ist high the integrated dc/dc driv er is active. the driver stage is self-protected in overload condition: the internal switches will be turned off as long as the overcurr ent condition is detected and the ic will automatically restart once t he overload condition disappears. important: since the uv and mv (as well as the te and w4s) bits used for generating the err signal are preset to high during uvlo, the err pin is low after power up. therefore the err signal requires to be explicitly cleared after power up. at least one read access to the glerr and interr registers is nee ded to update those status bits and thus release the err pin. v vbb v vbbuvon mv por_uv_mv_events .vsd v mv v reset v vbboff v vbbon v uv v vbbmvoff v vbbmvon v vbbuvoff time voltage v vbbhys v vbbhys v vbbhys rst uv
ISO1I813T functional description preliminary data sheet 16 v1.0, 2011-03-xx 3.2.2 external supply figure 4 shows the start up behaviour if both voltage domain s are powered by an external power supply. if the vcc and vbb voltage have reached their operating range and the internal data trans mission has been started successfully, the ic indicates the end of the start up procedure by setting the pin err to logic high figure 4 start up procedure with external power supply tds_ star tup _ timing_813 .vsd dc_ena vb b 9. 3 v ic pins int err register /err te dc_err w4s 13 v v c c 2. 85 v 16 v gl err register cf uv mv 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 t fistart 1 0 read access to adr. 04h 1 0 read access to adr. 16h
preliminary data sheet 17 v1.0, 2011-03-xx ISO1I813T functional description 3.2.3 dc/dc supply figure 5 typical circuitry for self powered mode with push-pull converter the ic can as well operate in self powered mode. in th is case, the process side can be supplied at vbb with an isolated push-pull converter connected to the micro-cont roller side and driven by the pins sw1 and sw2 . the internal driver stage at sw1 and sw2 is designed to power up two ISO1I813T (refer to table 8 ). the dc/dc- converter is driven by the internal clock. parameters are calculated with the internal clock = 500 khz. by setting the dck bit in the glcfg register a prescaler by 2 can be activated. should the user adjusts another different frequency the transformer has to be adjusted accordingly. the short-circuit protection uses a tem perature sensor located close to the dr ivers and disables the driver stages when a predefined temperature is reached ( figure 7 , figure 5 ). the target value for the switch-off-temperature is 160c with a hysteresis of < 10c. that means that th e drivers are switched off at a temperature of 160 c and switched on at a temperature of <=150c pp output driver sense-domain uc-domain clk vcc gnd sw1 sw2 gndbb vbb uc supply (5v / 3.3v) uc supply (gnd) n1 n2 tr dc_ena dcdc _typapp . vsd vcc temp. sense : 2 dck
ISO1I813T functional description preliminary data sheet 18 v1.0, 2011-03-xx figure 6 start up procedure with dc/dc supply tds _star tupdcdc _timing _813 . vsd dc_ena v b b 9. 3 v ic pins int err register /err te dc_err w4s 13 v v c c 2. 85 v 16 v gl err register cf uv mv 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 t vbbfil t fistart 1 0 read access to adr. 16h
preliminary data sheet 19 v1.0, 2011-03-xx ISO1I813T functional description figure 7 restart procedure after vbb drop due to dc/dc supply overtemperature uc_dcovt _timing_813. vsd dc_ena vbb 9. 3 v ic pins int err register /err te sense-chip power-up sense-chip shut down sense-chip restart dc_err w4s 8 v overtempera- ture detected at dc-dc read access to adr. 16h sw1, sw2 restart after returning from ot
ISO1I813T functional description preliminary data sheet 20 v1.0, 2011-03-xx 3.3 internal oscillator an external resistor has to be connected to rosc an d allows the adjustment of the frequency as shown in figure 8 . figure 8 internal frequency setting at rosc the internal oscillator provides the sc an clock for the sampling of the sensor data and diagnostics as well as the internal digital averaging filters. theref ore the filter times as defined in the table 11 for the typical frequency of 500 khz will change accordingly. as an ex ample, it is possible to define filt er time longer th an 20 ms by reducing the internal oscillator frequency. moreover, in the applications where the ic current consumpt ion is critical, it is poss ible to reduce the internal oscillator frequency by increasing the r osc (see figure 9 ). figure 9 ic current consumption in function of the internal frequency 0 100 200 300 400 500 600 0 50 100 150 200 250 resistance at rosc (kohm) khz 0 2 4 6 8 10 12 0 100 200 300 400 500 600 ct_frequency [khz] supply current [ma] sense chip 24v uc chip 5v uc chip 3.3v
preliminary data sheet 21 v1.0, 2011-03-xx ISO1I813T functional description 3.4 sensor input 3.4.1 input type select the sensor input structures are shown in figure 10 . due to its active current a v-i-characteristic as shown in figure 11 is maintained. this v-i-curve is well within the iec 61131 standard requirements of type 1, type 2 and type 3 sensors, respectively. the figure 12 shows the typical application for s ensor of type 2. it is recommended to choose for the external resistors r ext , r v , r led an accuracy of 2 % (< 5% is mandatory) otherwise the v/i- characteristic shown in figure 11 cannot be guaranteed. figure 10 typical application for sensor input type 1, 2 and 3 12k (8.5k *) 2k (1, 5k *) inx ixh ixl datax ma statusx v fi vbb gndbb sensor x x = 1,...,8 *) : for type2 r ts ts r wb wb
ISO1I813T functional description preliminary data sheet 22 v1.0, 2011-03-xx figure 11 sensor input characteristics figure 12 typical application for sensor type 2 -3v 5v 15v/11v i inxopen 0. 5ma 2ma/3ma 15ma v inxdset v inxdclr i inxsnkc,m v fi =30v 01 00 10 10 00 00 data bit must be zero data bit must be one 10 data bit = 1, status bit = 0 active current sink "open" v inxdhys c e.g. xe166 i0h i0l gndbb i1h i1l vbb vcc ts /err /cs gnd s e r i a l i z e d e s e r i a l i z e l o g i c ISO1I813T parallel or serial interface digital filter digital filter 4 sensors only 1.5k 8,2k 1k 330n 1.5k 8,2k in0 in1 v fi gndfi sync wb sw1 sw2 dc ena i7h i7l ... rosc
preliminary data sheet 23 v1.0, 2011-03-xx ISO1I813T functional description 3.4.2 wire break detection the wire-break current can be adjusted by the r wb -resistor value connected to the pin wb ( figure 13 ). the minimum wirebreak-current can be choo sen only when a led- or zener-diode is connected to the pin ixl with a forward current in the range of few ua in the voltage range below 1 v. in the case of a connected resistor at ixl a great current is flowing acro ss the external resistor re xt and the ixl-resistor (r led ). this part cannot be measured internally and has to be added to the internal current part. in this case the minimum adjustable current is greater by about 150ua (r led = 2kohm). the wb bits in the status register have a sticky (latched) property and remains set as long as they are not cleared by a read ac cess and the fault condition is not detected anymore figure 13 wire break detection for type 1,3 (typ. @ 25c) wire-break-current versus rwb 0 50 100 150 200 250 300 350 400 450 25 30 35 40 45 50 55 rwb[kohm] wire-break-current[ua] wbmin_led wbmax_led wbmin_rled wbmax_rled
ISO1I813T functional description preliminary data sheet 24 v1.0, 2011-03-xx figure 14 wire break detection for type 2 (typ. @ 25c) in the case of type 2 two sense inputs are switched in parallel to achieve 2 * 3 ma ( figure 12 ). in each sense input a mimimum wirebreak current of 60 ua can be me asured which means in sum a minimum wirebreak current of 120 ua. it is not recommended to use external resistors at the pins ixl in case of wirebreak measurements. the recommended value would be r led = 1.2 kohm which has been choosen in order not to produce a large voltage drop between ixl and gndbb which in tu rn would limit the voltage drop acro ss the sink. but the low value of r led would cause a high external current in case of wirebrea k-measurements which has to be multiplied by two due to the parallel circuitry of the sense inputs. 3.5 common error output the input (vbb) undervoltage and miss ing voltage status whic h are transmitted via the integrated coreless transformer to the output block and the internal data tr ansmission monitoring information are evaluated in the common error output block, see figure 15 . in self-powered mode, an extra information in case of over-current at sw1/2 is evaluated as well. in case of an internal data transmission error the data and status bits are replaced by the last valid transmission. moreover, if four consecutive erroneou s data transmissions (te1=1) occur, an internal error signal (te4=1) is set. the averaging filters are reset and this status is held unt il four consecutive error-free transmissions (te1=0) occur. an example timing diagram is shown in figure 15 . this internal error signal is or- wired with the curren t vbb undervoltage and missing vo ltage status. additionaly in the ISO1I813T, the collective diag nostics flag is combined in the err . since the output error signal is low- active, the or-wired result is negated. in the self powered mode, the uv and mv ar e masked out. instead the dc_err bit of the interr is combined with the transmission error sig nal and output at the err pin. wire-break-current versus rwb 0 100 200 300 400 500 600 700 800 25 30 35 40 45 50 55 rwb[kohm] wire-break-current[ua] wbmin_led wbmax_led wbmin_rled wbmax_rled
preliminary data sheet 25 v1.0, 2011-03-xx ISO1I813T functional description the output stage at pin err has an open drain functionality with a pull-up resistor. see table 13 for the electrical characteristics. figure 15 common error output filter n o r scan trigger transmission error uv trig te 1 te1 te4 vbb undervoltage trig te 4 0123 0123 /err mv vbb missing voltage (w/ parallel interface only ) cf collective diagnostics error /err 1 dc_err dc_ena mux dc/dc converter error w4s wait for sense
ISO1I813T functional description preliminary data sheet 26 v1.0, 2011-03-xx 3.6 programmable digital input filter the sensor data and diagnose bits of each input channel can be filtered by a configur able digital input filter. if selected, the filter changes its output according to an averaging rule with a selectable average length. when the sensor state changes without any spikes and noise the change is delayed by the averaging length. sensor spikes that are shorter than the averaging length are suppressed. figure 16 shows the behavior of the filter. figure 16 digital filter behavior the averaging length is selected for each channe l individually using the configuration registers coefil0-7 . the programmed filter time apply for both the da ta and the diagnostics of one channel. see table 11 for the different setting options including filter bypass. in this case, a minimal processing time occurs until the new configuration and the filtered data are valid and can e.g. be frozen with the pin sync (described in figure 17 and table 17 ). figure 17 filter time programming and update timing whereas the absolute filter time dep ends on the internal os cillator frequency accura cy, the maximal jitter per channel of the ic is 1.5 %. the channel jitter defined in the figure 18 is due to the sampling error of the sensor data with the internal clock and applies equally for all the channels. furthermore, a fixed propagation delay has to be taken into account due to the data transmission over the coreless transformer. scan trigger filter input filter output filter state output is 1 output is 0 output is unchanged 0 1 2 n-1 n-2 averaging time n-3 t filrdy /cs sclk sdi sdo wr/adr03 coef3 coef4 diag inpdata inpdata wr/adr04 diag coeff _ timing3. vsd sync t filwr xx coef4 rd/adr04 t filrd t rd inpdata spi mode 2
preliminary data sheet 27 v1.0, 2011-03-xx ISO1I813T functional description figure 18 channel jitter definition 3.7 parallel interface mode the ISO1I813T contains a parallel inte rface that can be selected by pulling the sel pin to logic low state. the interface can be directly controlled by the microcontroller output ports. ( figure 19 ). the output pins ad7:ad0 are in state ?z? as long as cs =1. otherwise, new sensor data bits or status bits are sampled with the rising edge of rd , and driven by the falling edge of wr and provided at pins ad7:ad0. figure 19 bus configuration for parallel mode the timing requirements for the parallel interface are shown in figure 20 , figure 21 and table 15 . channel input (e.g. in0) filter output channel jitter at filter input (internal ) t ctdelay t fil (e.g. 3,2 ms) jitter _timing.vsd t chnjitter int. clock t /cs sclk sdo t chrdy data valid vcc /cs /rd, /wr ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ISO1I813T mcu (e.g. c166) or asic parallel _interface 1.vsd vcc ale sel
ISO1I813T functional description preliminary data sheet 28 v1.0, 2011-03-xx figure 20 parallel bus timing read figure 21 parallel bus timing write rd_timing_813t - uc _parallel /cs ad[7:0] t advalid ale /rd t ad_hd t rdlow t rdhigh t rd_su t float t rd_hd t cl rrdy 00 h glerr glerr address (04 h) glerr data t ad_su glerr data t csd w r_ timing_813 t - uc_ parallel /cs ad[7:0] ale /wr t ad_hd t wrhigh t wr_su t wr_hd t lat coefilx coefilx address t ad_su t dat_hd t dat_su 00 h 0fh t csd coefilx data 0fh coefilx data 0ah
preliminary data sheet 29 v1.0, 2011-03-xx ISO1I813T functional description 3.8 serial interface mode the ISO1I813T contains two serial interfaces that can be activated by pulling the sel pin to logic high state. the interface can be directly controlled by the microcontroller output ports. the output pins sdo and sso are in state ?z? as long as cs =1. otherwise, the bits are sa mpled with the falling edge of cs . with every falling edge of sclk the bits are provided serially to the pin sdo and sso, res pectively. at the same time, the inputs to sdi, ssi are registered into input-fifo buffers (sampled with the rising edge of sclk). when all internally sampled bits have been transferred to sdo/sso, the buffered bits from the i nputs sdi/ssi are provided to these pins (daisy-chain support). the timing requirements for the serial interface are shown in figure 22 and in table 16 . figure 22 serial bus timing several spi topologies are supported: pure bus topology, daisy-chain and any combinations ( figure 23 ). of course independent individual control wit h dedicated spi controller interfaces for each slave ic is possible, as well. figure 23 example spi topologies serial_ bus_ timing transmit edge receive edge t sclk _valid msb t su t hd /cs sclk sdi, ssi sdo, sso lsb msb lsb t csd t float t cs_valid inactive active t sclk t sclk _su t csh sclk /cs sdo sso a sclk /cs sdo sso b sclk /cs sdo sso c sclk /cs sdo sso d sclk /cs sdo sdi a sclk /cs sdo sdi b sclk /cs sdo sdi c sclk /cs sdo sdi d mcu or asic sclk miso0 mcu or asic sclk miso0 miso1 spi_topologies .vsd sclk sso sdo sdi a d mcu or asic sclk miso0 /cs ssi sclk sso sdo sdi d /cs ssi mosi0 mosi0
ISO1I813T functional description preliminary data sheet 30 v1.0, 2011-03-xx 3.8.1 spi modes 3.8.1.1 switching serial modes all serial modes ms1, ms0 = 11, 01, 10, 00 are switchabl e during operation but not within a serial transfer frame. no internal registers are affected. on ly multiplexers and crc-engines can be activated or deactivated. internal fsms are reset. the user has to run one dummy serial pr ocess after switching of seri al modes to clear the serial shift registers and reset the internal fsms. for example: switching from ms1, ms0 = 00 to ms1, ms0 = 11 means the 24 bit serial shift registers an d the crc-engines will be activated. to guarantee proper operation one dummy read sequence has to be processed means ?shift in 24 bits with read address, zeros and crc within a cs = low frame? to operate the serial interface in the new mode . a reliable output is not guaranteed for the first serial process. the same is true for changing the serial mode in the reverse direction : from ms1, ms0 = 11 to ms1, ms0 = 00. here at least one serial access (8 sclk-cycles) within a cs =low frame is necessary. be aware that in mode01 read access the data at sd o/sso corresponds to the adress which has been written in the frame before. mode00 and mode 01 support the daisy-chain application. figure 24 spi mode 0 cs sclk sso sdo chip select active msb d7 d6 d5 d4 d3 d2 d0 d1 input-value collective diagnosis msb mode 0: ms0:=0, ms1:=0; 8 bit access; daisy-chain supported wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1
preliminary data sheet 31 v1.0, 2011-03-xx ISO1I813T functional description figure 25 spi mode 1 cs sclk sdi chip select active msb msb value 1 (valid on write) mode 1: ms0:=1, ms1:=0; 16 bit access; daisy-chain supported sdo wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1 d7 d6 d5 d4 d3 d2 d0 d1 input-value write command d7 d6 d5 d4 d3 d2 d0 d1 register-adress 1 collective diagnosis msb msb uv mv cf global error bits msb msb sso collective diagnosis sdo d7 d6 d5 d4 d3 d2 d0 d1 input-value register data 1 msb msb msb msb sso collective diagnosis d7 d6 d5 d4 d3 d2 d0 d1 sdi msb msb read command register-adress 1 register data 2 d7 d6 d5 d4 d3 d2 d0 d1 wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1 wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1 1 a5a4a3a2 a0 a1 0 a5a4a3a2 a0 a1 w4s dc_ err internal error bits 00 0000000 0 a6 a6 ssi msb msb value 2 (valid on write) d7 d6 d5 d4 d3 d2 d0 d1 register-adress 2 1 a5a4a3a2 a0 a1 a6 msb msb register-adress 2 0 a5a4a3a2 a0 a1 0000000 0 a6 ssi te addressed in the former frame
ISO1I813T functional description preliminary data sheet 32 v1.0, 2011-03-xx figure 26 spi mode 2 cs sclk sdi 1 chip select active a5 a4 a3 a2 a0 a1 d7 d6 d5 d4 d3 d2 d0 d1 register-adress 1 msb msb mode 2: ms0:=0, ms1:=1; 16 bit access; no daisy-chain supported sdo input data value 1 (valid on write ) msb msb sso global error bits msb msb write command collective diagnosis d7 d6 d5 d4 d3 d2 d0 d1 collective diagnosis uv mv cf sdi 0 a5 a4 a3 a2 a0 a1 register-adress 1 msb msb sdo input data msb msb sso register data 2 msb msb read command collective diagnosis d7 d6 d5 d4 d3 d2 d0 d1 register data 1 d7 d6 d5 d4 d3 d2 d0 d1 d7 d6 d5 d4 d3 d2 d0 d1 wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1 wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1 wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1 w4s dc_ err te 00 0 000 0 0 a6 a6 ssi 1 a5 a4 a3 a2 a0 a1 d7 d6 d5 d4 d3 d2 d0 d1 register-adress 2 msb msb value 2 (valid on write) a6 ssi 0 a5 a4 a3 a2 a0 a1 register-adress 2 msb msb 00 0 000 0 0 a6 00 internal error bits
preliminary data sheet 33 v1.0, 2011-03-xx ISO1I813T functional description figure 27 spi mode 3 the error values in the sdo-segment depend on the settin g of dc_ena. if dc_ena is set to 1 the ic is supplied by the integrated dc/dc converter and the error informa tion w4s, dc_err, cf is valid. if dc_ena is set to 0 the error information uv, mv, cf is valid sso cs sclk sdi 1 chip select active a5 a4 a3 a2 a0 a1 d7 d6 d5 d4 d3 d2 d0 d1 register-adress 1 msb msb mode 3: ms0:=1, ms1:=1; 24 bit access; no daisy-chain supported sdo d7 d6 d5 d4 d3 d2 d0 d1 input-data collective diagnosis value 1 (valid on write) msb uv mv cf c4 c3 c2 c0 c1 checksum 3 0 0 0 c4c3c2 c0 c1 checksum 1 write command msb msb msb msb collective diagnosis uv mv cf global error sso sdi 0 a5 a4 a3 a2 a0 a1 000000 0 0 register-adress 1 msb msb sdo d7 d6 d5 d4 d3 d2 d0 d1 input-data msb uv mv cf c4 c3 c2 c0 c1 error * checksum 3 c4 c3 c2 c0 c1 checksum 1 read command msb msb msb msb collective diagnosis d7 d6 d5 d4 d3 d2 d0 d1 d7 d6 d5 d4 d3 d2 d0 d1 register-data 1 register-data 2 wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1 wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1 wb7 wb6 wb5 wb4 wb3 wb2 wb0 wb1 w4s dc_ err te w4 s dc_ err cf w4 s dc_ err cf internal error 00 c4 c3 c2 c0 c1 global config checksum 4 error * glc2 glc1 glc0 00 0 c4 c3 c2 c0 c1 global config checksum 4 glc2 glc1 glc0 a6 a6 ssi 1 a5 a4 a3 a2 a0 a1 d7 d6 d5 d4 d3 d2 d0 d1 register-adress 2 msb msb value 2 (valid on write) msb 000c4c3c2 c0 c1 checksum 2 a6 ssi 0 a5 a4 a3 a2 a0 a1 000000 0 0 register-adress 2 msb msb msb c4 c3 c2 c0 c1 checksum 2 00 0 a6 *) dc_ena = 0 , upper values dc_ena = 1 , lower values
ISO1I813T functional description preliminary data sheet 34 v1.0, 2011-03-xx 3.8.2 architecture of crc-engines for writing serial data into the uc-i nterface chip one serial-spi-mode (ms1, ms0 = 11) delivers with the pure input data bit stream (write by an uc, 19 bits ) also the crc-signature (5 bi ts). the total bitstrea m is fed into the crc- input engines and processed according to the underlying crc-algorithm serially. the crc is a 5-bit-checksum and will be calculated with the polynom x5+ x4 + x2+1 and is calculated from bit [23:5]. the checksum is transfered to bi t [4:0]. after totally processed 24 seria lly shifted in-bits (including the crc- signature) the total result of the crc-algorithm processing has to be zero. in the case of another result different from zero the delivered sign ature is not consistent with the delivered bit stream. this will be indicated by setting the crc_err pin to low for reading of registers by a uc a cr c-signature (5 bits) (ms1, ms0 = 11) w ill be delivered with the pure data bit stream (19 bits) : data outp ut (read by a uc). the read bitstream has to be processed according to the crc- algorithm serially. after totally processed 19 serially sh ifted out-bits the crc-signat ure has been calculated and delivered to the output pins sdo, sso. 3.9 sync operation the filtered data and diagnostics can be synchronized on the fallin g edge of the sync pin or ?frozen? by holding sync low (see figure 28 and table 17 ). figure 28 sync operation timing sync_timing.vsd /cs filtered data int. clock sync channel input t syncw t syncmi n t synccon t syncper
preliminary data sheet 35 v1.0, 2011-03-xx ISO1I813T standard compliance 4 standard compliance the ISO1I813T allows the design of a sensor interface compliant with the standard requirements listed below: system insulation characteristics as shown in table 3 , system immunity characteristics as shown in table 5 . these requirements are valid for an application using th e ISO1I813T including external circuitry (as proposed in figure 29 ), not for the ic alone. note: when the ic is not supplie d, probing of the sensor inpu t interface is still possible due to the external circuitry, i.e. the 12k resistor and the led. in addition to the current through the led a small current i ixh flows through the pins ixh and ixl. figure 29 recommended application circuit figure 30 system insulation characteristics table 2 system absolute maximum ratings parameter symbol values unit note / test condition min. typ. max. field input voltage overvoltage 1300 ms v fiov -45 +45 v input voltage inx v inx -45 +45 v c e.g. xe166 i0h i0l gndbb i7h i7l vbb vcc ts /err gnd s e r i a l i z e d e s e r i a l i z e l o g i c ISO1I813T parallel or serial interface digital filter digital filter 8 sensors 2k 12k 330n 2k 12k in0 in7 v fi gndfi sync wb sw1 sw2 dc ena /cs rosc +? io v iso r io ,c io
ISO1I813T standard compliance preliminary data sheet 36 v1.0, 2011-03-xx table 3 system insulation characteristics parameter symbol values unit note / test condition min. typ. max. pollution degree (din vde 0110/1.89, din en 60664-1) 2 minimum external clearance clr 6.7 mm minimum external creepage cpg 6.2 mm comparative tracking index cti 550 v maximum working insulation voltage v iso 500 v ac 1min duration 1) 1) not subject to production test, verified by characterization approval ul1577 pending approval csa pending approval en61131-2 pending
preliminary data sheet 37 v1.0, 2011-03-xx ISO1I813T electrical characteristics 5 electrical characteristics this section comprises: ? operating conditions and power supply (see section 5.2 ) ? electrical characteristics input side (see section 5.3 ) ? electrical characteristics microcontroller interface (see section 5.4 ) tolerance values always contain the sum of process-rela ted tolerance values and tolerance-values based on the temperature drift within the specified temperature range. 5.1 absolute maximum ratings all voltages at pins 25 to 48 are measured with respect to ground gndbb. all voltages at pins 1 to 24 are measured with respect to gnd. the vo ltage levels are valid if other ratings are not violated. the two voltage domains vcc, gnd and vbb, gndbb are internally electrically isolated. stresses above those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stress rating only and functional operation of the devi ce at these or any other conditions above those indicated in the operational sections of this spec ification is not implied. exposure to absolute maxi mum rating conditions for extended periods may af fect device reliability. table 4 absolute maximum ratings parameter symbol value unit note / test condition min. max. continuous voltage at pin vbb v vbb -0.3 45 v power dissipation must not exceed max-value peak voltage vbb, overvoltage 500 ms v vbb -0.3 45 v supply voltage vcc v vcc -0.3 6.5 v continuous voltage at logic pins 1 - 24 (except vcc and gnd pins) v log -0.3 6.5 v continuous voltage at pin ts, wb -0.3 6.5 v junction temperature t j -40 150 c storage temperature t s -50 150 c power dissipation p tot 800 mw input voltage range v ixh -45 45 v input voltage range v ixl -0.3 5 v error pin sink current (err =0) i errsink 5mav err < 0.25v vcc error pin sink current (crcerr =0) i crcsink 5mav err < 0.25v vcc dc-dc switch outputs 1/2 sw1/2 20 v electrostatic discharge voltage (human body model) according to jesd22-a114-b v esd ??2.5kv electrostatic discharge voltage (charge device model) according to esd stm5.3.1 - 1999 v esd ??1.5kv
ISO1I813T electrical characteristics preliminary data sheet 38 v1.0, 2011-03-xx 5.2 operating conditions and power supply for proper operation of the device, absolute maximum rating ( section 4 ) and the parameter ranges in table 5 must not be violated. exceeding the limits of operating condition parameters may result in device malfunction or spec violations. the power su pply pins vbb and vcc have t he characteristics given in table 7 . table 5 operating range parameter at t j = -40 ... 125c symbol value unit note / test condition min. max. supply voltage logic vcc v vcc 2.85 5.5 v related to gnd supply voltage senses vbb v vbb 9.6 35 v related to gndbb continuous vbb voltage in self-power mode v vbbdc 12 16 v see figure 4 for operation points) 1) 1) recommended for operation ambient temperature t a -40 85 c junction temperature t j -40 125 c common mode transient dv iso /dt -25 25 kv/ s magnetic field immunity |h im | 30 a/m iec61000-4-8 table 6 thermal characteristics parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol limit values unit note / test condition min. max. thermal resistance junction - case top r thjc_top 15.0 k/w measured on top side) 1) 1) not subject to production test, specified by design thermal resistance junction - case bottom r thjc_bot 13.8 k/w ) 1) thermal resistance junction - pin r thjp 11.8 k/w ) 1) thermal resistance @ 2 cm2 cooling area 2) (thermal conductance only by radiation and free convection) 2) device on 50 mm x 50 mm x 1.5 mm epoxy pcb fr4 with 2 cm2 (one layer, 35 m thick) copper area. pcb is vertical without blow air. r th(ja) 88.6 k/w ) 1) table 7 electrical characteristics of the power supply pins parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. vbb uvlo startup threshold v vbbon 9.6 v vbb uvlo shutdown threshold v vbboff 8.0 v ) 1) vbb uvlo hysteresis v vbbhys 1v vbb missing voltage off (mv) threshold v vbbmvoff 13.9 v vbb missing voltage on (mv) threshold v vbbmvon 12.1 v
preliminary data sheet 39 v1.0, 2011-03-xx ISO1I813T electrical characteristics vbb undervoltage off (uv) threshold v vbbuvoff 17.0 v vbb undervoltage voltage on (uv) threshold v vbbuvon 15.0 v glitch filters for vbb missing voltage and undervoltage t vbbfil 8s) 2) undervoltage current for vbb i vbbuv 3.5 ma v vbb < v vbbon quiescent current vbb i vbbq 5mav vbb = 24 v, i inx = 0, vcc = 2.5v startup delay (time between vbbon/vccon and first data output) t vxxon 26 s digital filter bypassed) )2 3) vcc uvlo startup threshold v vccon 2.85 v vcc uvlo shutdown threshold v vccoff 2.5 v ) 4) vcc uvlo threshold hysteresis v vcchys 0.1 v ) )2 5) quiescent current vcc i vccq 3.1 ma v vcc = 5 v) 2) 5) v vbb = 0v quiescent current vcc i vccq 2.3 ma v vcc = 3.3 v v vbb = 0v 1) note that the specified oper ation of the ic requires v vbb as given in table 5 2) defined for f scantyp 500khz 3) not subject to production test, specified by design 4) note that the specified oper ation of the ic requires v vcc as given in table 5 5) no push-pull converter connected at sw1/2 table 8 self-powered supply operation parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. on resistance at sw1/2 r dson 2.3 ? 140 ma current rating i sw 140 ma thermal overload trip temperature t jt 157 165 c ) 1) 1) not subject to production test, specified by design thermal hysteresis ? t jt 5k) 1) table 7 electrical characteristics of the power supply pins (cont?d) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max.
ISO1I813T electrical characteristics preliminary data sheet 40 v1.0, 2011-03-xx 5.3 electrical charact eristics input side the electrical characteristics of the input side (pins 25-48) are given in table 9 . note that some parameters refer to in0 to in7 which are nodes of external circuitry (see figure 10 or figure 29 ). electrical characteristics with respect to these nodes are given for the system including the external ci rcuitry and not for the ic alone. see also figure 11 for the different threshold parameters. table 9 sensors inputs parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. sink current limit at saturation edge type 1/3 i inxsnkc13 2.3 ma v vbb =v vbbon , v inx =6.7v, v ixl = 1.2v sink current limit at saturation edge type 2 i inxsnkc2 3.3 ma v vbb =v vbbon , v inx =6.7v, v ixl =1. 2v sink current limit at maximum input voltage type 1/3 i inxsnkm13 3.4 ma v vbb =35v, v inx =30v, v ixl = 2.5v sink current limit at maximum input voltage type 2 i inxsnkm2 4.8 ma v vbb =35v, v inx =30v, v ixl = 2.5v led supply current at maximum input voltage, type 1/3 i ixlmax 2.1 3.1 ma v vbb =35v, v inx =30v, v ixl = 2.5v led supply current at maximum input voltage, type 2 i ixlmax 3.1 4.5 ma v vbb =35v, v inx =30v, v ixl = 2.5v led supply current at high threshold type 3 i ixl1 1.5 2.5 ma v vbb =v vbbon , v inx =11v, v ixl = 2.5v led supply current at high threshold type 2 i ixl2 2.3 3.6 ma v vbb =v vbbon , v inx =11v, v ixl = 2.5v led supply current at high threshold type 1 i ixl3 1.6 2.6 ma v vbb =v vbbon , v inx =15v, v ixl = 2.5v led voltage recommended v fled 1.9 3.0 v ) 1) sense voltage switching threshold, l h (type 1) v inxdset(1) 15 v vbb =24v v ixl = 2.5v) 2) sense voltage switching threshold h l (type 1) v inxdclr(1) 11 v vbb =24v v ixl = 2.5v) 2) hysteresis h ? l (type 1) v inxdhys(1) 1 sense voltage switching threshold l h (type 2) v inxdset(2) 11 v vbb =24v v ixl = 2.5v) 2) sense voltage switching threshold h l (type 2) v inxdclr(2) 7v vbb =24v v ixl = 2.5v) 2) hysteresis h ? l (type 2) v inxdhys(2) 0.65 sense voltage switching threshold l h (type 3) v inxdset(3) 11 v vbb =24v v ixl = 2.5v) 2) sense voltage switching threshold h l (type 3) v inxdclr(3) 7v vbb =24v v ixl = 2.5v) 2)
preliminary data sheet 41 v1.0, 2011-03-xx ISO1I813T electrical characteristics hysteresis h ? l (type 3) v inxdhys(3) 0.7 input sink current when v vbb =0 i ixhq 300 a v vbb =0v v ixh =30v , ixl = open 1) not subject to production test, specified by design 2) clamped to 2.5v if ?logic 1?, internally limited if logic ?0? table 10 setting at the configuration pins (ts, wb) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. ts pull-down resistance for type 1 selection r tspd1 33 ? ) 1) 1) required for operation ts pull-down resistance for type 2 selection r tspd2 33 k ? 2) 1) 2) only 4 channels can be used for this case. ts pull-down resistance for type 3 selection r tspd3 330 k ? ) 1) wb pin source current i wbsource 12.5 a r wb = 40k ? wb pin detection current i wb 80 a r wb = 40k ? wirebreak detection blanking time t wb_blank 1s) 3) 4) 3) not subject to production test, specified by design 4) defined for f scantyp 500khz type selection blanking time t ts_blank 2s) 3) 4) max. wb pin load capacitance c wbmax 5pf) 1) max. ts pin load capacitance c tsmax 20 pf ) 1) table 9 sensors inputs (cont?d) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max.
ISO1I813T electrical characteristics preliminary data sheet 42 v1.0, 2011-03-xx 5.4 electrical characteristics microcontroller interface for the parallel mode see table 11 , table 12 , table 14 and table 15 , for the serial mode see table 11 , table 12 , table 14 and table 16 . timing characteristics refer to c l < 50 pf and r l >10k ? . table 11 sensor scanning and averaging 1) 1) valid for f scantyp = 500khz parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. typical scan frequency f scantyp 440 510 khz r osc =22.1k ? without tolerance scan frequency range f scanrge 50 500 khz ) 2) refer to figure 8 2) not subject to production test, specified by design input scan propagation delay t ctdelay 8s) 1) applies equally to all channels filter bypass delay t bypass 2s) 1) minimal filter output valid time (until readout i.e. cs falling edge) t csrdy 1.2 s including maximum channel jitter) 1) channel jitter 3) 3) the channel jitter is defined in figure 18 t chnjitter 0 2 s s for t filt00 and t filt01 ) 1) channel jitter t chnjitter 0 1.5 % for t filt02 to t filt07 ) 1) digital filter monitoring time t filt00 0.050 ms ft=00 h ) 1) digital filter monitoring time t filt01 0.100 ms ft=01 h ) 1) digital filter monitoring time t filt02 0.400 ms ft=02 h ) 1) digital filter monitoring time t filt03 0.800 ms ft=03 h ) 1) digital filter monitoring time t filt04 1.600 ms ft=04 h ) 1) digital filter monitoring time t filt05 3.200 ms ft=05 h ) 1) digital filter monitoring time t filt06 10.000 ms ft=06 h ) 1) digital filter monitoring time t filt07 20.000 ms ft=07 h ) 1) digital filter monitoring time t filtoff 2.0 s ft=08 h ..0f h ) 1) table 12 setting at the configuration pin (rosc) see also figure 8 parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. rosc pin source current i roscsrc 50 a r osc =22.1k ? rosc resistance to gnd r rosc 18.4 22.1 221 k ? e96 resistor rosc pin regulated voltage v roscreg 1.2 v max. rosc pin load capacitance c roscmax 5pf) 1) 1) required for operation
preliminary data sheet 43 v1.0, 2011-03-xx ISO1I813T electrical characteristics table 13 error pins (err , crcerr ) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. error pin pull-up resistance (err =1) r errpu 50 k ? maximum switching frequency (err , crcerr ) f sw 10 500 khz ) 1) 1) not subject to production test, specified by design error pin low voltage v errol 0.25v vcc vi errol = 5ma table 14 logical pins (rd , w r , ale, ms0/1, cs , ad7:ad0, sclk, sdo, sso, sdi, ssi, sel) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. input voltage high level v ih 0.7v vcc v vcc +0.3 v input voltage low level v il -0.3 0.3v vcc v input voltage hysteresis v ihys 100 mv output voltage high level v oh 0.75v vcc 1v vcc vi oh = 5ma output voltage low level v ol 00.25v vcc vi ol = 5ma table 15 parallel interface parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. input pull up resistance (rd , wr , cs ) r pu 50 k ? input pull down resistance (ale) r pd 50 k ? read request frequency f rd 0.06 9 mhz read request period (1/f rd )t rd 110 15000 ns cs disable time (minimum cs high time between two accesses) t csd 7s valid ad0-7 output t adout 55 55 ns vcc = 3.3v vcc = 5.0v ad0-7 setup time related to wr t dat_su 25 ns ad0-7 hold time related to wr t dat_hd 25 ns r d setup time t rd_su 55 ns w r setup time t wr_su 55 ns r d low duration t rdlow 55 ns vcc = 3.3v vcc = 5.0v
ISO1I813T electrical characteristics preliminary data sheet 44 v1.0, 2011-03-xx w r low duration t wrlow 55 ns vcc = 3.3v vcc = 5.0v r d hold time t rd_hd 020 ns w r hold time t wr_hd 020 ns r d pad to diag, glerr and interr registers update (bits clearing) t clrrdy 46.2s ad0-7 output disable time t float 30 ns vcc = 5.0v ad0-7 data bus setup time t ad_su 40 ns ad0-7 data bus hold time t ad_hd 50 ns wr latency time tlat 600 4800 ns table 16 serial interface parameter at t j = -25 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. input pull up re sistance ( c s )r pu 50 k ? input pull down resistance (sclk, sdi) r pd 50 k ? serial clock frequency f sclk 9 10 mhz vcc = 3.3v vcc = 5.0v serial clock period (1/f sclk )t sclk 110 100 ns vcc = 3.3v vcc = 5.0v serial clock high period t sclkh 55 50 ns vcc = 3.3v vcc = 5.0v serial clock low period t sclkl 55 50 ns vcc = 3.3v vcc = 5.0v minimum cs hold time (rising edge of sclk to rising edge of cs ) t csh 40 ns minimum cs disable time (cs high time between two accesses) t csd 4.8 s ) 1) minimum data setup time (required time sdi to rising edge of sclk) t su 5ns minimum data hold time (rising edge of sclk to sdi) t hd 15 ns minimum valid time cs falling edge to output sdo/sso t cs_valid 50 ns c s falling edge to first rising sclk edge t sclk_su 80 ns table 15 parallel interface (cont?d) parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max.
preliminary data sheet 45 v1.0, 2011-03-xx ISO1I813T electrical characteristics minimum valid time sclk falling edge to output sdo/sso t sclk_valid 80 70 ns vcc = 3.3v vcc = 5.0v minimum sdo/sso output disable time t float 50 65 ns vcc = 3.3v vcc = 5.0v new serial mode activation time (ms0/ms1 change to earliest interface access) t ms_rdy 4 s no controller access allowed during the change) 1) 2) 1) valid for f scantyp = 500khz 2) not subject to production test, specified by design table 17 sync and coefficient update timing parameter at t j = -40 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max. minimum time interval for c- read-access after falling edge of sync-signal t syncmin 500 ns minimum time interval for switching from sync mode into the continuous mode t synccon 3s minimum width of sync-signal t sync 200 ns sync-period t syncper 500 ns minimum time interval between 2 write cycles for filter time programming t filwr 4s) 1) 1) valid for f scantyp = 500khz minimum time interval between a write cycle and a read back cycle for filter time programming t filrr 4s) 1) minimum time interval between a filter time write cycle and updated filter data freeze t filrdy 4s) 1) table 16 serial interface (cont?d) parameter at t j = -25 ... 125c, v bb =9.6...35v, v cc =2.85...5.5v, unless otherwise specified symbol values unit note / test condition min. typ. max.
ISO1I813T registers of microcontroller-interface-chip preliminary data sheet 46 v1.0, 2011-03-30 , 6 registers of microc ontroller-interface-chip this chapter describes the controller chip registers. 6.1 controller chip registers overview the table 6-2 gives an overview of the controller chip registers and their address. table 6-1 register bit type definition type symbol description read r the bit can be read read only, updated by hardware h the bit is updated by the device itself (f or instance: sticky bit) write w the bit can be written table 6-2 registers summary short name description access rights 1) 1) r=read-only, rw=read-write (timing restri ctions apply), rh=read update by hardware address a6-a0, r/w diag collective diagnostics register (wire-break detection) rh 00 h inpdata input data register (i nput channel data) r 02 h glerr global error register rh 04 h coefil0 ( coefil0-7 ) filter time for the data and the diagnostics of channel 0 rw 06 h , 86 h coefil1 filter time for the data and the diagnostics of channel 1 rw 08 h , 88 h coefil2 filter time for the data and the diagnostics of channel 2 rw 0a h , 8a h coefil3 filter time for the data and the diagnostics of channel 3 rw 0c h , 8c h coefil4 filter time for the data and the diagnostics of channel 4 rw 0e h , 8e h coefil5 filter time for the data and the diagnostics of channel 5 rw 10 h , 90 h coefil6 filter time for the data and the diagnostics of channel 6 rw 12 h , 92 h coefil7 filter time for the data and the diagnostics of channel 7 rw 14 h , 94 h interr internal error register rh 16 h glcfg global configuration register rw 1c h reserved n.a. other
preliminary data sheet 47 v1.0, 2011-03-30 , ISO1I813T registers of microcontroller-interface-chip 6.2 presentation of the registers the controller side chip provides several 8-bit register s which can be accessed by th e controller over the serial or parallel interface. since those registers are located in the chip internal clock do main, the access is controlled by an internal arbiter processing the read / write reque sts as well as the synchronization requirements especially to freeze the internal registers when the isochronous mode is used (sync pin). some timing requirements apply to guarantee the data consistency provided to the controller (see electrical characterisitcs). 6.2.1 sensor registers the sensor data and status (wire-break) detected at the c hannel inputs ixh/l by the s ensor side chip are available in the inpdata and diag registers respectively. the bits of the diag register have a sticky property i.e.once a wire-break condition has been detected (after the filter ti me), the respective bits re main set. a read access resets the sticky bits under the condition, that no wirebreak is de tected anymore. in the serial modes, both registers are per default driven out at the spo/sso outputs. 6.2.2 status registers the glerr and interr registers contains t he status of the ic. glerr monitors the application relevant parameters: undervoltage (uv), missing voltage (mv) and collective fault (cf) whereas interr indicates the status of internal signals important for the proper operatio n of the ic: wait for sense chip (w4s), transmission error (te) and dc-dc error (dc_err) in case of self powered mode. those registers can be read over the serial or parallel interface especially to identify the fault causing the error pin (err) to be pulled down. there are different options to read those registers: either through direct addressing (e.g. parallel mode) or through the telegram mode when the serial interface is selected where the bits are shifted out during the transaction. the bits of the glerr and interr registers have a sticky property and remains set as long as they are not cleared by a read access and the fault condition is not detected anymore. the table 6-3 presents which bits are cleared depending on the serial mode and the spi channel. in the case of the parallel interface, the bits cleared are the ones whose address is contained in the internal ale register. only the bits having been read can be cleared. since the bits are frozen when a read access is de tected, it is guaranted that only these bits read over the serial or parallel interfac e can be cleared: if the status of the bits changes during the tran saction, they will not be cleared. table 6-3 clear of the sticky bits by serial interface mode 0 mode 1 mode 2 mode 3 read / write read read write read write read write spi channel-0 n.a. rdreg 1) diag rdreg 1) 1) the bits of register which is being read (direct addressing) diag rdreg 1) uv, mv, w4s, dc_err) 2) 2) depends on setting of dc_ena diag uv, mv, w4s, dc_err) 2) spi channel-1 diag diag rdreg 1) diag uv, mv, w4s, te, dc_err diag rdreg 1) diag uv, mv, w4s, te, dc_err diag rdreg 1) diag uv, mv, w4s, te, dc_err
ISO1I813T registers of microcontroller-interface-chip preliminary data sheet 48 v1.0, 2011-03-30 , 6.2.3 configuration registers the filter times of each chan nel can be programmed with the coefil0-7 registers. since the write access requires some time to update the internal registers, specific timing requirements apply es pecially between 2 successive programming operations. the coefil0-7 registers define as well if the wire break detection should be masked or not in the diag register. only one of the coefilx registers can be written at th e same time (in serial mode only one spi channel can be used). it is possible to program a filt er time and simultaneously to read ou t another register e.g. another channel filter time. furthermore, the behavior of the ic can be customized with the glcfg register: ? the ratio of the switching frequency of the dc-dc oupu t stage over the internal clock frequency set at the clkadj pin can be changed from 1:1 (default) to 2:1. ? a soft reset can be generated to clear the filter sta ges and reinitialize the data transmission between sense side and controller side chips. ? the automatical clearing of the diag when the register is read without direct addressing can be disabled.
preliminary data sheet 49 v1.0, 2011-03-30 , ISO1I813T registers of microcontroller-interface-chip 6.3 controller registers description 6.3.1 collective di agnostics register this register contains the filtered values of the wire-break detection of the channels 0 to 7. this register can be read by the controller. the wb[x] ar e set with the occurence of a wire break at input line x and can only be cleared by a read operation of this regist er if the wire break is not de tected anymore (sticky bits). as soon as one of those bits is set, the cf-bit of the glerr is set as well.the chapter 6.2.2 explains the way the sticky bits are cleared. 6.3.2 input channel data register this register contains the filtered values of the input data detected at the channels 0 to 7. this register can be read by the controller. when the parallel interface is selected, the default addre ss contained in the internal ale register is the address of this register. diag collective diagnostics register (address : 00 h ) reset value: 00 h 76543210 wb7 wb6 wb5 wb4 wb3 wb2 wb1 wb0 rh field bits type description wb[x] 7-0 rh channel wire-break detected this bit indicates if a wire-break has been detected at the channel x. 0 b no wire-break signal detected at channel x. 1 b a wire-break condition has been detected at channel x. inpdata input data register (address : 02 h ) reset value: 00 h 76543210 d7 d6 d5 d4 d3 d2 d1 d0 rh field bits type description d[x] 7-0 rh input channel data this bit represents the input data dete cted at the pins ixh of the channel x depending on the sensor type selected. 0 b input data below the input threshold. 1 b input data above the input threshold.
ISO1I813T registers of microcontroller-interface-chip preliminary data sheet 50 v1.0, 2011-03-30 , 6.3.3 global error register this register contains the status of th e ic parameters monitored during operation. this register can only be read by the controller. the cf-bit is the or-combination of all the bits of the diag register. the bits of this register ar e sticky and can only be cleared when the bits are read out and the faults are not detected anymore (refer to chapter 6.2.2 for more details). the uv and mv bits are reset to 1 when the vbb voltage is below the uvlo th reshold or during transmission error between the sensor side and c ontroller side. the bits of the glerr register are used in the generation of the signal of the error pin (err ) and shifted out in some of the serial modes when the spi interface is selected. glerr global error register (address : 04 h ) reset value: 06 h 76543210 0uvmvcf rrh field bits type description cf 0rh channel fault this bit indicates that at least one wire- break condition has been detected at the channel inputs. 0 b no wire-break condition has been detected at the channels . 1 b at least one channel shows a wire-break condition . mv 1rh vbb missing voltage this bit indicates if a missing voltage c ondition has been detected at the vbb pin. 0 b no missing volta ge detected at vbb. 1 b a missing voltage condition has been detected at vbb. uv 2rh vbb under voltage this bit indicates if an undervoltage condition has been detected at the vbb pin. 0 b no undervoltage detected at vbb. 1 b an undervoltage has been detected at vbb. 0 [7:3] r reserved returns 0 if read.
preliminary data sheet 51 v1.0, 2011-03-30 , ISO1I813T registers of microcontroller-interface-chip 6.3.4 filter time of channel 0-7 register this register defines the filt er time for both the data and diagnostics fo r each channel in0-7. it configures as well if the wire-break bit must be masked in the diag register. this register can be modified and read by the controller. . coefil0-7 channel 0-7 filter time register (address : 06 h - 14 h for read access, 86 h - 94 h for write access , ) reset value: 1f h 76543210 000mwb ft rrw rw field bits type description ft [3:0] rw filter time this bit field configures the filter time for averaging the data and the wire-break signals detected at channels in0-7. 00 h 50 s 01 h 100 s 02 h 400 s 03 h 800 s 04 h 1,6 ms 05 h 3,2 ms 06 h 10 ms 07 h 20 ms 08 h - 0f h bypassed (default) mwb 4rw mask wire-break detection this bit masks the filtered signa l of the wire-break detection. 0 b the wire-break signal is masked and is not visible in the diag register. 1 b the wire-break signal is not masked and appears in the diag register. (default). 0 [7:5] r reserved returns 0 if read; should be written with 0.
ISO1I813T registers of microcontroller-interface-chip preliminary data sheet 52 v1.0, 2011-03-30 , 6.3.5 internal error register this register contains the status of the internal errors monitored for safe ic operation. the bits are sticky and remain set once the fault condition is detected until a re ad operation occurs and the faults are resolved. the bits of the interr register are used in the generation of the erro r pin (err) and shifted out in some of the serial modes when the spi interface is sele cted. on power up (uvlo), the bits w4s and te are preset to high and will have to be cleared by a read access during the startup phase. interr ic status register (address : 16 h ) reset value: 06 h 76543210 0w4ste dc_ err rrh field bits type description dc_err 0rh dc-dc converter error this bit indicates if overload condition has been detected at the sw1 or sw2 switches. 0 b no overload detected. 1 b overload detected. te 1rh transmission error this bit indicates if a transmission e rror has been detected over the coreless transformer between the sense side chip and the controller side chip. 0 b no transmission error. 1 b transmission error. w4s 2rh wait for sense chip this bit indicates the sense side chip is correctly supplied and ready for transmission. 0 b sense side is ready. 1 b sense side is not ready because of insu fficient supply or long transmission error. 00000 [7:3] r reserved returns 0 if read.
preliminary data sheet 53 v1.0, 2011-03-30 , ISO1I813T registers of microcontroller-interface-chip 6.3.6 global config uration register this register contains configuration parameters for the sensor type selection as well as the dc-dc driver. glcfg global configuration register (address : 1c h ) reset value: 00 h 76543210 0 diag aclr sw_r st dck 0 rrwrwrwr field bits type description 00 1:0 rw reserved returns 0 if read; should be written with 0. dck 2rw dc-dc driver switching frequency ratio this bit indicates the ratio between the sampling clock frequency set at rosc and the switching frequency of the dc-dc driver (pins sw1/2). 0 b dc-dc switching frequency is equal to the sampling frequency (1:1) (default). 1 b dc-dc switching frequen cy is half to the sampling frequency (2:1). sw_rst 3rw soft-reset for the filtering stage this bit triggers the reset of the filter registers 0 b no reset 1 b reset is generated for the filter stage diag_aclr 4rw diagnostics automatical clear this bit selects if the diag register is automatically cleared after any access to the diag register (especially for the second spi channel at the sso pin). the diagnostics remain in both case sticky. 0 b automatical clear after any access to the diag register (default) 1 b automatical clear disabled 000 [7:5] r reserved returns 0 if read; should be written with 0.
confidential iso1i811t package outline preliminary data sheet 54 v1.0, 2011-03-18 , 7 package outline figure 7-1 package outline tssop-48 (tie bar not drawn in outline) notes 1. you can find all of our packages, sorts of packing an d others in our infineon internet page ?products?: http://www.infineon.com/products . 2. dimensions in mm.
published by infineon technologies ag www.infineon.com

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